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Searched refs:RISCV_IOMMU_REG_MSI_CONFIG (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-pci.c107 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, in riscv_iommu_pci_realize()
108 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); in riscv_iommu_pci_realize()
H A Driscv-iommu-bits.h212 #define RISCV_IOMMU_REG_MSI_CONFIG 0x0300 macro
H A Driscv-iommu.c1937 if (addr + size > RISCV_IOMMU_REG_MSI_CONFIG) { in riscv_iommu_mmio_write()
2035 if (addr + size > RISCV_IOMMU_REG_MSI_CONFIG) { in riscv_iommu_mmio_read()