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Searched refs:RISCV_IOMMU_REG_FQH (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h129 #define RISCV_IOMMU_REG_FQH 0x0030 macro
H A Driscv-iommu.c118 uint32_t head = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQH) & s->fq_mask; in riscv_iommu_fault()
1736 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask); in riscv_iommu_process_fq_control()
1737 stl_le_p(&s->regs_rw[RISCV_IOMMU_REG_FQH], 0); in riscv_iommu_process_fq_control()
1743 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~0); in riscv_iommu_process_fq_control()