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Searched refs:RISCV_IOMMU_REG_FQCSR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/tests/qtest/
H A Driscv-iommu-test.c70 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_FQCSR); in test_reg_reset()
174 reg = riscv_iommu_read_reg32(r_iommu, RISCV_IOMMU_REG_FQCSR); in test_iommu_init_queues()
176 riscv_iommu_write_reg32(r_iommu, RISCV_IOMMU_REG_FQCSR, reg); in test_iommu_init_queues()
178 qtest_wait_for_queue_active(r_iommu, RISCV_IOMMU_REG_FQCSR); in test_iommu_init_queues()
/openbmc/qemu/tests/qtest/libqos/
H A Driscv-iommu.h51 #define RISCV_IOMMU_REG_FQCSR 0x004C macro
/openbmc/qemu/hw/riscv/
H A Driscv-iommu.c117 uint32_t ctrl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQCSR); in riscv_iommu_fault()
132 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, in riscv_iommu_fault()
138 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, in riscv_iommu_fault()
1727 uint32_t ctrl_set = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQCSR); in riscv_iommu_process_fq_control()
1751 riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, ctrl_set, ctrl_clr); in riscv_iommu_process_fq_control()
1874 fqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQCSR); in riscv_iommu_update_ipsr()
1960 case RISCV_IOMMU_REG_FQCSR: in riscv_iommu_mmio_write()
2183 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_FQCSR], RISCV_IOMMU_FQCSR_FQMF | in riscv_iommu_realize()
2185 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQCSR], RISCV_IOMMU_FQCSR_FQON | in riscv_iommu_realize()
H A Driscv-iommu-bits.h157 #define RISCV_IOMMU_REG_FQCSR 0x004C macro