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Searched refs:RISCV_IOMMU_PPN_FIELD (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h57 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) macro
101 #define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD
115 #define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD
126 #define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD
137 #define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD
202 #define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD
217 #define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD
413 #define RISCV_IOMMU_MSI_PTE_PPN RISCV_IOMMU_PPN_FIELD
418 #define RISCV_IOMMU_MSI_MRIF_NPPN RISCV_IOMMU_PPN_FIELD