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Searched refs:RISCV_IOMMU_MSI_PTE_M (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h405 #define RISCV_IOMMU_MSI_PTE_M GENMASK_ULL(2, 1) macro
H A Driscv-iommu.c585 switch (get_field(pte[0], RISCV_IOMMU_MSI_PTE_M)) { in riscv_iommu_msi_write()