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Searched refs:RISCV_IOMMU_CMD_IOFENCE_AV (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu-bits.h285 #define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10) macro
H A Driscv-iommu.c1577 cmd.dword0 & RISCV_IOMMU_CMD_IOFENCE_AV, cmd.dword1 << 2, in riscv_iommu_process_cq_tail()