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Searched refs:REG_PHY_PHASE_OFFS (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c118 (reg >> REG_PHY_PHASE_OFFS) & in ddr3_write_leveling_hw()
438 (reg >> REG_PHY_PHASE_OFFS) & in ddr3_wl_supplement()
541 (reg >> REG_PHY_PHASE_OFFS) & in ddr3_write_leveling_hw_reg_dimm()
H A Dddr3_axp.h311 #define REG_PHY_PHASE_OFFS 8 macro
H A Dddr3_hw_training.c557 reg |= (phase << REG_PHY_PHASE_OFFS) | delay; in ddr3_write_pup_reg()
H A Dddr3_read_leveling.c108 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()