Home
last modified time | relevance | path

Searched refs:QCA955X_PLL_DDR_CONFIG_REG (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/arch/mips/ath79/
H A Dclock.c465 pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG); in qca955x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h481 #define QCA955X_PLL_DDR_CONFIG_REG 0x04 macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h391 #define QCA955X_PLL_DDR_CONFIG_REG 0x04 macro