Home
last modified time | relevance | path

Searched refs:PLL_BASE_ENABLE (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c16 #define PLL_BASE_ENABLE BIT(30) macro
353 return val & PLL_BASE_ENABLE ? 1 : 0; in clk_pll_is_enabled()
379 val |= PLL_BASE_ENABLE; in _clk_pll_enable()
397 val &= ~PLL_BASE_ENABLE; in _clk_pll_disable()
1008 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); in clk_plle_enable()
1855 if (val & PLL_BASE_ENABLE) { in _clk_plle_tegra_init_parent()
2085 if (val & PLL_BASE_ENABLE) in tegra_clk_register_pllxc()
2129 if (val & PLL_BASE_ENABLE) in tegra_clk_register_pllre()
2386 if (val & PLL_BASE_ENABLE) { in tegra_clk_register_pllss()