/openbmc/openbmc/meta-openembedded/meta-oe/recipes-networking/cyrus-sasl/cyrus-sasl/ |
H A D | debian_patches_0014_avoid_pic_overwrite.diff | 6 Description: This patch makes sure the non-PIC version of libsasldb.a, which 7 is created out of non-PIC objects, is not going to overwrite the PIC version, 8 which is created out of PIC objects. The PIC version is placed in .libs, and 9 the non-PIC version in the current directory. This ensures that both non-PIC 10 and PIC versions are available in the correct locations.
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | open-pic.txt | 1 * Open PIC Binding 4 representation of an Open PIC compliant interrupt controller. This binding is 5 based on the binding defined for Open PIC in [1] and is a superset of that 13 - compatible: Specifies the compatibility list for the PIC. The type 20 as an Open PIC. No property value shall be defined. 31 - pic-no-reset: The presence of this property indicates that the PIC 55 * An Open PIC interrupt controller 62 // this Open PIC node do not need a parent address specifier. 71 // Compatible with Open PIC. 74 // The PIC shall not be reset. [all …]
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H A D | marvell,armada-8k-pic.txt | 1 Marvell Armada 7K/8K PIC Interrupt controller 4 This is the Device Tree binding for the PIC, a secondary interrupt 13 - reg: the register area for the PIC interrupt controller
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H A D | intel,ce4100-lapic.yaml | 46 PIC Mode - Legacy external 8259 compliant PIC interrupt controller. 50 For OF based systems, it is by default set to PIC mode.
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H A D | loongson,pch-pic.yaml | 7 title: Loongson PCH PIC Controller 27 to PCH PIC.
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H A D | cdns,xtensa-mx.txt | 6 Remaining properties have exact same meaning as in Xtensa PIC
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H A D | google,goldfish-pic.txt | 1 Android Goldfish PIC
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/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/ |
H A D | irq-chip-model.rst | 15 HTVECINTC(Hyper-Transport Vector Interrupt Controller)、PCH-PIC(LS7A芯片组的主中 19 全局中断控制器(每个芯片一个,所有核共享),而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中 27 CPU串口(UARTs)中断发送到LIOINTC,而其他所有设备的中断则分别发送到所连接的PCH-PIC/ 46 | PCH-PIC | | PCH-MSI | 63 CPU串口(UARTs)中断发送到LIOINTC,而其他所有设备的中断则分别发送到所连接的PCH-PIC/ 77 | PCH-PIC | | PCH-MSI | 117 PCH-PIC:: 156 - PCH-PIC/PCH-MSI:即《龙芯7A1000桥片用户手册》第5章所描述的“中断控制器”;
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | ep8248e.dts | 72 interrupt-parent = <&PIC>; 77 interrupt-parent = <&PIC>; 135 interrupt-parent = <&PIC>; 148 interrupt-parent = <&PIC>; 161 interrupt-parent = <&PIC>; 174 interrupt-parent = <&PIC>; 186 interrupt-parent = <&PIC>; 192 PIC: interrupt-controller@10c00 { label
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H A D | mgcoge.dts | 140 interrupt-parent = <&PIC>; 153 interrupt-parent = <&PIC>; 164 interrupt-parent = <&PIC>; 194 interrupt-parent = <&PIC>; 207 interrupt-parent = <&PIC>; 218 interrupt-parent = <&PIC>; 226 interrupt-parent = <&PIC>; 246 PIC: interrupt-controller@10c00 { label
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H A D | mpc885ads.dts | 32 interrupt-parent = <&PIC>; 103 interrupt-parent = <&PIC>; 115 interrupt-parent = <&PIC>; 120 PIC: interrupt-controller@0 { label 134 interrupt-parent = <&PIC>; 171 interrupt-parent = <&PIC>; 228 interrupt-parent = <&PIC>;
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H A D | tqm8xx.dts | 39 interrupt-parent = <&PIC>; 73 interrupt-parent = <&PIC>; 85 interrupt-parent = <&PIC>; 115 interrupt-parent = <&PIC>; 120 PIC: pic@0 { label 161 interrupt-parent = <&PIC>;
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H A D | ep88xc.dts | 32 interrupt-parent = <&PIC>; 98 interrupt-parent = <&PIC>; 110 interrupt-parent = <&PIC>; 115 PIC: interrupt-controller@0 { label 129 interrupt-parent = <&PIC>; 165 interrupt-parent = <&PIC>;
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H A D | adder875-redboot.dts | 37 interrupt-parent = <&PIC>; 100 interrupt-parent = <&PIC>; 112 interrupt-parent = <&PIC>; 117 PIC: interrupt-controller@0 { label 156 interrupt-parent = <&PIC>;
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H A D | adder875-uboot.dts | 37 interrupt-parent = <&PIC>; 99 interrupt-parent = <&PIC>; 111 interrupt-parent = <&PIC>; 116 PIC: interrupt-controller@0 { label 155 interrupt-parent = <&PIC>;
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H A D | mpc866ads.dts | 32 interrupt-parent = <&PIC>; 83 interrupt-parent = <&PIC>; 88 PIC: pic@0 { label 129 interrupt-parent = <&PIC>;
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H A D | gamecube.dts | 50 interrupt-parent = <&PIC>; 62 PIC: pic { label
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/openbmc/linux/Documentation/arch/loongarch/ |
H A D | irq-chip-model.rst | 11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller 15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e., 24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go 43 | PCH-PIC | | PCH-MSI | 61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to 75 | PCH-PIC | | PCH-MSI | 115 PCH-PIC:: 157 - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
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/openbmc/openbmc/poky/meta/recipes-extended/zip/zip-3.0/ |
H A D | 0002-configure-support-PIC-code-build.patch | 4 Subject: [PATCH 2/2] configure: support PIC code build 26 + # disable match.S for PIC code
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/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/ |
H A D | 0003-apic-fixup-fallthrough-to-PIC.patch | 4 Subject: [PATCH 03/12] apic: fixup fallthrough to PIC 6 Commit 0e21e12bb311c4c1095d0269dc2ef81196ccb60a [Don't route PIC
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/openbmc/qemu/tests/tcg/mips/ |
H A D | Makefile.target | 17 hello-mips: CFLAGS+=-mno-abicalls -fno-PIC -fno-stack-protector -mabi=32
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
H A D | usb.txt | 13 interrupt-parent = <&PIC>;
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/openbmc/qemu/docs/system/arm/ |
H A D | mainstone.rst | 13 - PIC
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/openbmc/qemu/docs/system/openrisc/ |
H A D | cpu-features.rst | 10 - Programmable Interrupt Controller (PIC)
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/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/tinyalsa/ |
H A D | tinyalsa_2.0.0.bb | 18 # tinyalsa is built as a static library. Enable PIC to avoid relocation
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