Searched refs:PHYCLKD18PerState (Results 1 – 7 of 7) sorted by relevance
251 double PHYCLKD18PerState,
1338 double PHYCLKD18PerState, in dml32_CalculateOutputLink() argument
2089 mode_lib->vba.PHYCLKD18PerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
1088 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; member
399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()
4342 v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {4358 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&4384 v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {4400 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&4426 v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
4431 v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {4447 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&4473 v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {4489 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&4515 v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {