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Searched refs:PEXTDEV (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/video/fbdev/riva/
H A Dnvreg.h98 #define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
99 #define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
100 #define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
101 #define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
102 #define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
103 #define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
H A Driva_hw.c627 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv3UpdateArbitrationSettings()
814 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv4UpdateArbitrationSettings()
1065 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? in nv10UpdateArbitrationSettings()
1993 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv3GetConfig()
2050 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; in nv4GetConfig()
2134 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
2148 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
H A Dnv_driver.c326 par->riva.PEXTDEV = in riva_common_setup()
H A Driva_hw.h450 volatile U032 __iomem *PEXTDEV; member
/openbmc/linux/drivers/video/fbdev/nvidia/
H A Dnv_setup.c220 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ? in nv4GetConfig()
258 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? in nv10GetConfig()
262 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22)) in nv10GetConfig()
301 par->PEXTDEV = par->REGS + (0x00101000 / 4); in NVCommonSetup()
H A Dnv_type.h162 volatile u32 __iomem *PEXTDEV; member
H A Dnv_hw.c395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv4UpdateArbitrationSettings()
635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv10UpdateArbitrationSettings()