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Searched refs:MSR_TS0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dcpu.h429 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */ macro
478 FIELD(MSR, TS0, MSR_TS0, 1)
480 FIELD(MSR, TS, MSR_TS0, 2)
H A Dcpu_init.c6366 (1ull << MSR_TS0) | in POWERPC_FAMILY()