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Searched refs:MSRSET (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/microblaze/cpu/
H A Dcache.c32 MSRSET(0x20); in icache_enable()
42 MSRSET(0x80); in dcache_enable()
H A Dinterrupts.c22 MSRSET(0x2); in enable_interrupts()
/openbmc/u-boot/arch/microblaze/include/asm/
H A Dasm.h53 #define MSRSET(val) \ macro
60 #define MSRSET(val) \ macro