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Searched refs:MSG_PORT_HOST_BRIDGE (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/x86/cpu/quark/
H A Dquark.c27 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000, in quark_setup_mtrr()
29 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000, in quark_setup_mtrr()
33 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000, in quark_setup_mtrr()
35 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000, in quark_setup_mtrr()
37 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000, in quark_setup_mtrr()
39 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000, in quark_setup_mtrr()
42 msg_port_write(MSG_PORT_HOST_BRIDGE, i, in quark_setup_mtrr()
48 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM), in quark_setup_mtrr()
62 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE, in quark_setup_mtrr()
101 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, in quark_setup_bars()
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H A Ddram.c146 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), in dram_init()
148 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), in dram_init()
H A Dcar.S26 mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dquark.h11 #define MSG_PORT_HOST_BRIDGE 0x03 macro