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Searched refs:MSCC_QS_INJ_WR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Dmscc_xfer.c36 writel(ifh[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
39 writel(buff[i], regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
43 writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
53 writel(0, regs + mscc_qs_offset[MSCC_QS_INJ_WR]); in mscc_send()
H A Dmscc_xfer.h12 MSCC_QS_INJ_WR, enumerator
H A Docelot_switch.c133 [MSCC_QS_INJ_WR] = 0x2c,
H A Dluton_switch.c200 [MSCC_QS_INJ_WR] = 0x3c,