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Searched refs:MPCTL0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/arm920t/imx/
H A Dspeed.c40 u32 mpctl0 = MPCTL0; in get_mcuPLLCLK()
/openbmc/u-boot/board/armadeus/apf27/
H A Dlowlevel_init.S40 write32 MPCTL0, ACFG_MPCTL0_VAL
/openbmc/u-boot/arch/arm/lib/
H A Dasm-offsets.c81 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h101 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ macro