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Searched refs:MMU_INST_FETCH (Results 1 – 25 of 40) sorted by relevance

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/openbmc/qemu/target/ppc/
H A Dmmu-booke.c167 if ((access_type == MMU_INST_FETCH ? in mmubooke_check_tlb()
185 return access_type == MMU_INST_FETCH ? -3 : -2; in mmubooke_check_tlb()
348 if (access_type == MMU_INST_FETCH) { in mmubooke206_check_tlb()
387 return access_type == MMU_INST_FETCH ? -3 : -2; in mmubooke206_check_tlb()
430 if (access_type == MMU_INST_FETCH) { in booke206_update_mas_tlb_miss()
509 cs->exception_index = (access_type == MMU_INST_FETCH) ? in ppc_booke_xlate()
516 cs->exception_index = (access_type == MMU_INST_FETCH) ? in ppc_booke_xlate()
518 if (access_type != MMU_INST_FETCH) { in ppc_booke_xlate()
H A Dmmu-hash32.c57 bool ifetch = access_type == MMU_INST_FETCH; in ppc_hash32_bat_lookup()
124 if (access_type == MMU_INST_FETCH) { in ppc_hash32_direct_store()
323 if (access_type == MMU_INST_FETCH) { in ppc_hash32_xlate()
354 if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) { in ppc_hash32_xlate()
366 if (access_type == MMU_INST_FETCH) { in ppc_hash32_xlate()
393 if (access_type == MMU_INST_FETCH) { in ppc_hash32_xlate()
H A Dmmu-radix64.c122 case MMU_INST_FETCH: in ppc_radix64_raise_segi()
155 case MMU_INST_FETCH: in ppc_radix64_raise_si()
194 case MMU_INST_FETCH: in ppc_radix64_raise_hsi()
240 if ((pte & R_PTE_ATT) == R_PTE_ATT_NI_IO && access_type == MMU_INST_FETCH) { in ppc_radix64_check_prot()
264 *fault_cause |= access_type == MMU_INST_FETCH ? SRR1_NOEXEC_GUARD : in ppc_radix64_check_prot()
280 case MMU_INST_FETCH: in ppc_radix64_check_rc()
H A Dmmu_common.c95 bool is_code = (access_type == MMU_INST_FETCH); in ppc6xx_tlb_check()
119 access_type == MMU_INST_FETCH ? 'I' : 'D'); in ppc6xx_tlb_check()
197 bool ifetch = access_type == MMU_INST_FETCH; in get_bat_6xx_tlb()
590 if (access_type == MMU_INST_FETCH ? !FIELD_EX64(env->msr, MSR, IR) in ppc_real_mode_xlate()
624 if (access_type == MMU_INST_FETCH) { in ppc_40x_xlate()
685 if (access_type == MMU_INST_FETCH) { in ppc_6xx_xlate()
864 ppc_xlate(cpu, addr, MMU_INST_FETCH, &raddr, &s, &p, in ppc_cpu_get_phys_page_debug()
H A Duser_only_helper.c40 if (access_type == MMU_INST_FETCH) { in ppc_cpu_record_sigsegv()
H A Dmmu-hash64.c1045 case MMU_INST_FETCH: in ppc_hash64_xlate()
1084 case MMU_INST_FETCH: in ppc_hash64_xlate()
1103 if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { in ppc_hash64_xlate()
1117 case MMU_INST_FETCH: in ppc_hash64_xlate()
1149 if (access_type == MMU_INST_FETCH) { in ppc_hash64_xlate()
/openbmc/qemu/include/exec/
H A Dmmu-access-type.h14 MMU_INST_FETCH = 2 enumerator
/openbmc/qemu/target/microblaze/
H A Dhelper.c32 if (access_type == MMU_INST_FETCH) { in mb_cpu_access_is_secure()
84 env->esr = access_type == MMU_INST_FETCH ? 17 : 16; in mb_cpu_tlb_fill()
88 env->esr = access_type == MMU_INST_FETCH ? 19 : 18; in mb_cpu_tlb_fill()
H A Dop_helper.c408 access_type == MMU_INST_FETCH ? "INST_FETCH" : in mb_cpu_transaction_failed()
415 if (access_type == MMU_INST_FETCH) { in mb_cpu_transaction_failed()
/openbmc/qemu/target/arm/tcg/
H A Dtlb_helper.c187 bool is_vncr = (access_type != MMU_INST_FETCH) && in arm_deliver_fault()
201 access_type == MMU_INST_FETCH, in arm_deliver_fault()
245 if (access_type == MMU_INST_FETCH) { in arm_deliver_fault()
/openbmc/qemu/target/cris/
H A Dmmu.c156 case MMU_INST_FETCH: in cris_mmu_translate_page()
229 } else if (access_type == MMU_INST_FETCH && cfg_x && !tlb_x) { in cris_mmu_translate_page()
333 env->pregs[PR_SRS] = access_type == MMU_INST_FETCH ? 1 : 2; in cris_mmu_translate()
H A Dhelper.c249 miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1); in cris_cpu_get_phys_page_debug()
/openbmc/qemu/target/mips/tcg/
H A Dop_helper.c294 if (access_type == MMU_INST_FETCH) { in mips_cpu_do_unaligned_access()
311 if (access_type == MMU_INST_FETCH) { in mips_cpu_do_transaction_failed()
/openbmc/qemu/accel/tcg/
H A Duser-exec.c96 return MMU_INST_FETCH; in adjust_signal_pc()
798 case MMU_INST_FETCH: in probe_access_internal()
855 flags = probe_access_internal(env, addr, 1, MMU_INST_FETCH, false, 0); in get_page_addr_code_hostp()
1184 haddr = cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); in cpu_ldb_code_mmu()
1196 haddr = cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); in cpu_ldw_code_mmu()
1211 haddr = cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); in cpu_ldl_code_mmu()
H A Dcputlb.c111 MMU_INST_FETCH * sizeof(uint64_t)); in tlb_read_idx()
1178 MMU_INST_FETCH, prot & PAGE_EXEC); in tlb_set_page_full()
1382 || (access_type != MMU_INST_FETCH && force_mmio)) { in probe_access_internal()
1524 (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, in get_page_addr_code_hostp()
2896 return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH); in cpu_ldub_code()
2903 return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH); in cpu_lduw_code()
2910 return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH); in cpu_ldl_code()
2917 return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH); in cpu_ldq_code()
2923 return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); in cpu_ldb_code_mmu()
2929 return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); in cpu_ldw_code_mmu()
[all …]
/openbmc/qemu/target/s390x/
H A Dmmu_helper.c349 case MMU_INST_FETCH: in mmu_handle_skey()
449 if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) { in mmu_translate()
/openbmc/qemu/target/openrisc/
H A Dmmu.c122 int need = (access_type == MMU_INST_FETCH ? PAGE_EXEC in openrisc_cpu_tlb_fill()
/openbmc/qemu/target/loongarch/tcg/
H A Dtlb_helper.c57 cs->exception_index = access_type == MMU_INST_FETCH in raise_mmu_exception()
66 } else if (access_type == MMU_INST_FETCH) { in raise_mmu_exception()
77 } else if (access_type == MMU_INST_FETCH) { in raise_mmu_exception()
/openbmc/qemu/target/arm/
H A Dptw.c1232 if (xn && access_type == MMU_INST_FETCH) { in get_phys_addr_v6()
1262 access_type != MMU_INST_FETCH) { in get_phys_addr_v6()
1705 access_type != MMU_INST_FETCH, in get_phys_addr_lpae()
2231 if (access_type == MMU_INST_FETCH) { in get_phys_addr_pmsav5()
2774 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || in v8m_is_sau_exempt()
2806 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { in v8m_security_lookup()
2906 if (access_type == MMU_INST_FETCH) { in get_phys_addr_pmsav8()
3232 if (access_type == MMU_INST_FETCH) { in get_phys_addr_disabled()
3266 if (access_type == MMU_INST_FETCH) { in get_phys_addr_disabled()
/openbmc/qemu/tests/tcg/multiarch/
H A Dnoexec.c.inc2 * Common code for arch-specific MMU_INST_FETCH fault testing.
/openbmc/qemu/target/i386/tcg/sysemu/
H A Dexcp_helper.c478 assert(access_type != MMU_INST_FETCH); in mmu_translate()
493 case MMU_INST_FETCH: in mmu_translate()
/openbmc/qemu/target/loongarch/
H A Dcpu_helper.c55 if (access_type == MMU_INST_FETCH && tlb_nx) { in loongarch_map_tlb_entry()
/openbmc/qemu/target/xtensa/
H A Dhelper.c302 access_type == MMU_INST_FETCH ? in xtensa_cpu_do_transaction_failed()
/openbmc/qemu/target/alpha/
H A Dhelper.c141 case MMU_INST_FETCH: in alpha_cpu_record_sigsegv()
/openbmc/qemu/target/riscv/
H A Dcpu_helper.c1182 case MMU_INST_FETCH: in raise_mmu_exception()
1270 case MMU_INST_FETCH: in riscv_cpu_do_unaligned_access()
1294 case MMU_INST_FETCH: in pmu_tlb_fill_incr_ctr()

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