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Searched refs:MMSCH_V1_0_INSERT_DIRECT_WT (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c234 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), in vce_v4_0_sriov_start()
236 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), in vce_v4_0_sriov_start()
238 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), in vce_v4_0_sriov_start()
254 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
256 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
261 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
264 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
271 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
274 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
277 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
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H A Duvd_v7_0.c824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); in uvd_v7_0_sriov_start()
838 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), in uvd_v7_0_sriov_start()
857 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), in uvd_v7_0_sriov_start()
877 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
888 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), in uvd_v7_0_sriov_start()
897 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
901 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
917 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); in uvd_v7_0_sriov_start()
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H A Dvcn_v2_5.c1271 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1274 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1278 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1282 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1285 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1288 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1293 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1298 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1301 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
1308 MMSCH_V1_0_INSERT_DIRECT_WT( in vcn_v2_5_sriov_start()
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H A Dmmsch_v1_0.h138 #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \ macro