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Searched refs:MIP_VSSIP (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h728 #define MIP_VSSIP (1 << IRQ_VS_SOFT) macro
758 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
H A Dcpu_helper.c471 ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_mirq_pending()
480 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); in riscv_cpu_sirq_pending()
H A Dcsr.c1448 static const uint64_t hip_writable_mask = MIP_VSSIP;
1449 static const uint64_t hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
1453 static const uint64_t vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS;
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1007 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; in riscv_tcg_cpu_realize()