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Searched refs:MIN_POST_DIVR_FREQ (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c41 #define MIN_POST_DIVR_FREQ 7000000 macro
85 if (post_divr_freq < MIN_POST_DIVR_FREQ || in __wrpll_calc_filter_range()
192 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ) in __wrpll_update_parent_rate()
196 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ); in __wrpll_update_parent_rate()
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c48 #define MIN_POST_DIVR_FREQ 7000000 macro
94 if (post_divr_freq < MIN_POST_DIVR_FREQ || in __wrpll_calc_filter_range()
200 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ) in __wrpll_update_parent_rate()
204 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ); in __wrpll_update_parent_rate()