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Searched refs:MIDR (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/tools/perf/pmu-events/arch/nds32/
H A Dmapfile.csv2 # MIDR,Version,JSON/file/pathname,Type
5 # MIDR Processor version
/openbmc/linux/tools/perf/arch/arm64/util/
H A Dheader.c14 #define MIDR "/regs/identification/midr_el1" macro
34 scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d" MIDR, in _get_cpuid()
/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv2 # MIDR,Version,JSON/file/pathname,Type
5 # MIDR Processor version
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S239 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
/openbmc/linux/Documentation/arch/arm64/
H A Dcpu-feature-registers.rst77 MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex276 … uint64 & The CPU version information as reported by CPUID with EAX=1. On ARM, this is MIDR\_EL1.\\
726 midrEl1 & uint64 & The chip ID (\texttt{MIDR\_EL1}) for this error.\\
998 midr & uint64 & Register MIDR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\
1169 midr\_el1 & uint64 & Register MIDR (EL1).\\