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Searched refs:MAX_POST_DIVR_FREQ (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c51 #define MAX_POST_DIVR_FREQ 200000000 macro
95 post_divr_freq > MAX_POST_DIVR_FREQ) { in __wrpll_calc_filter_range()
208 c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1, in __wrpll_update_parent_rate()
209 MAX_POST_DIVR_FREQ); in __wrpll_update_parent_rate()
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c44 #define MAX_POST_DIVR_FREQ 200000000 macro
86 post_divr_freq > MAX_POST_DIVR_FREQ) { in __wrpll_calc_filter_range()
199 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ); in __wrpll_update_parent_rate()