Searched refs:J721E_CLK_PARENT_44100 (Results 1 – 1 of 1) sorted by relevance
33 #define J721E_CLK_PARENT_44100 1 macro184 clk_id = J721E_CLK_PARENT_44100; in j721e_configure_refclk()500 clocks->parent[J721E_CLK_PARENT_44100] = parent; in j721e_get_clocks()505 if (!clocks->parent[J721E_CLK_PARENT_44100] && in j721e_get_clocks()519 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */528 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */567 priv->pll_rates[J721E_CLK_PARENT_44100] = in j721e_calculate_rate_range()568 match_data->pll_rates[J721E_CLK_PARENT_44100]; in j721e_calculate_rate_range()583 if (!priv->pll_rates[J721E_CLK_PARENT_44100] && in j721e_calculate_rate_range()589 if (priv->pll_rates[J721E_CLK_PARENT_44100]) in j721e_calculate_rate_range()[all …]