/openbmc/u-boot/board/quipos/cairo/ |
H A D | cairo.h | 141 MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \ 142 MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \ 224 MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \ 225 MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \ 226 MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \ 227 MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \ 228 MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \ 229 MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \ 230 MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \ 231 MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \ [all …]
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/openbmc/u-boot/board/amazon/kc1/ |
H A D | kc1.h | 33 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ 34 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ 37 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ 51 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ 52 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ 54 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ 55 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ 56 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ 57 { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ 76 { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ [all …]
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/openbmc/u-boot/board/overo/ |
H A D | overo.h | 40 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ 41 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ 42 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ 50 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ 51 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ 52 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ 54 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ 55 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ 56 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ 79 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ [all …]
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H A D | common.c | 81 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ 82 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ 83 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ 84 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ 85 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ 86 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ 87 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ 88 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ 89 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ 90 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/compulab/cm_t3517/ |
H A D | mux.c | 57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs() 178 MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); in set_muxconf_regs() 179 MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); in set_muxconf_regs() [all …]
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/openbmc/u-boot/board/compulab/cm_t35/ |
H A D | cm_t35.c | 169 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in cm_t3x_set_common_muxconf() 170 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in cm_t3x_set_common_muxconf() 171 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in cm_t3x_set_common_muxconf() 172 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in cm_t3x_set_common_muxconf() 173 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in cm_t3x_set_common_muxconf() 174 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in cm_t3x_set_common_muxconf() 175 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in cm_t3x_set_common_muxconf() 176 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in cm_t3x_set_common_muxconf() 177 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in cm_t3x_set_common_muxconf() 210 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ in cm_t3x_set_common_muxconf() [all …]
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/openbmc/u-boot/board/timll/devkit8000/ |
H A D | devkit8000.h | 72 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 73 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 74 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 75 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 76 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 77 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 78 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 79 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 80 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 81 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/corscience/tricorder/ |
H A D | tricorder.h | 69 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 70 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 71 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 72 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 73 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 74 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 75 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 76 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\ 78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\ [all …]
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/openbmc/u-boot/board/ti/beagle/ |
H A D | beagle.h | 78 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 79 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 80 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 81 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 82 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 83 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 84 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 85 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 86 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 87 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/nokia/rx51/ |
H A D | rx51.h | 74 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 75 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 76 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 77 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 78 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 79 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 80 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 81 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 82 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 83 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/pandora/ |
H A D | pandora.h | 65 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 66 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 67 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 68 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 69 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 70 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 71 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 72 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 73 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 74 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/ti/evm/ |
H A D | evm.h | 88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ 89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ 90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ 91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ 92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ 93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ 94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ 95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ 96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ 97 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/technexion/twister/ |
H A D | twister.h | 91 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 92 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 93 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 94 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 95 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 96 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 97 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 98 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 99 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 100 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ [all …]
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/openbmc/u-boot/board/technexion/tao3530/ |
H A D | tao3530.h | 69 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 70 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 71 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 72 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 73 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 74 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 75 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 76 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ [all …]
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/openbmc/u-boot/board/isee/igep00x0/ |
H A D | igep00x0.h | 57 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ 58 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ 59 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ 60 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ 61 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ 62 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ 63 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ 64 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ 65 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ 66 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ [all …]
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/openbmc/u-boot/board/logicpd/am3517evm/ |
H A D | am3517evm.h | 82 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 87 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 89 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 90 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 91 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ [all …]
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/openbmc/u-boot/board/lg/sniper/ |
H A D | sniper.h | 53 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \ 55 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \ 56 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\ 58 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\ 78 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \ 87 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M7)) \ 88 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M7)) \ 89 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M7)) \ 92 MUX_VAL(CP(GPMC_NWP), (IDIS | PTD | DIS | M4)) /* gpio_62 */ \ 131 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /* gpio_98 */ \ [all …]
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/openbmc/u-boot/board/teejet/mt_ventoux/ |
H A D | mt_ventoux.h | 87 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 88 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 89 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 90 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 91 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 92 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 93 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 94 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 95 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 96 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ [all …]
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/openbmc/u-boot/board/logicpd/zoom1/ |
H A D | zoom1.h | 76 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ 77 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ 78 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ 79 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ 80 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ 81 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ 82 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ 83 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ 84 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ 85 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ [all …]
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/openbmc/u-boot/board/8dtech/eco5pk/ |
H A D | eco5pk.h | 79 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 80 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 81 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 82 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 83 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 84 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 85 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 86 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 87 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 88 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ [all …]
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/openbmc/u-boot/board/ti/am3517crane/ |
H A D | am3517crane.h | 83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\ 84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\ 85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\ 86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\ 88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\ 108 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\ 109 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\ 118 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\ 119 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\ 128 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\ [all …]
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/openbmc/u-boot/board/htkw/mcx/ |
H A D | mcx.h | 104 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ 116 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ 117 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ 121 MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ 129 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ 130 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ 131 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ 133 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ 134 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ 195 MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ [all …]
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/openbmc/u-boot/board/logicpd/omap3som/ |
H A D | omap3logic.h | 88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in set_muxconf_regs() 89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in set_muxconf_regs() 90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in set_muxconf_regs() 91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in set_muxconf_regs() 92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in set_muxconf_regs() 93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in set_muxconf_regs() 94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in set_muxconf_regs() 95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in set_muxconf_regs() 96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in set_muxconf_regs() 97 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ in set_muxconf_regs() [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-omap5/ |
H A D | mux_omap5.h | 33 #define IDIS (0 << 8) macro
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/openbmc/u-boot/arch/arm/include/asm/arch-omap4/ |
H A D | mux_omap4.h | 41 #define IDIS (0 << 8) macro
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