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Searched refs:ICPU_TIMER_VALUE (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h393 writel(val, BASE_CFG + ICPU_TIMER_VALUE(0)); in sleep_100ns()
400 while (readl(BASE_CFG + ICPU_TIMER_VALUE(0)) != 0) in sleep_100ns()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h71 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h65 #define ICPU_TIMER_VALUE(x) (0xe4 + 0x4 * (x)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h72 #define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h70 #define ICPU_TIMER_VALUE(x) (0xec + 0x4 * (x)) macro