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Searched refs:GPC_IMR1_CORE1 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dsoc.c29 #define GPC_IMR1_CORE1 0x40 macro
210 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4); in imx_gpcv2_init()
/openbmc/linux/drivers/irqchip/
H A Dirq-imx-gpcv2.c16 #define GPC_IMR1_CORE1 0x40 macro
263 writel_relaxed(~0, reg + GPC_IMR1_CORE1); in imx_gpcv2_irqchip_init()