Searched refs:GPC_IMR1_CORE0 (Results 1 – 3 of 3) sorted by relevance
21 #define GPC_IMR1_CORE0 0x30 macro351 val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()353 writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()358 val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()360 writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()369 val3 = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()371 writel(val3, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0); in imx_gpcv2_set_lpm_mode()565 imr[i] = readl(GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); in imx_system_resume()566 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); in imx_system_resume()588 writel(imr[i], GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); in imx_system_resume()[all …]
28 #define GPC_IMR1_CORE0 0x30 macro209 writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4); in imx_gpcv2_init()
15 #define GPC_IMR1_CORE0 0x30 macro262 writel_relaxed(~0, reg + GPC_IMR1_CORE0); in imx_gpcv2_irqchip_init()269 cd->cpu2wakeup = GPC_IMR1_CORE0; in imx_gpcv2_irqchip_init()