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Searched refs:G1_REG_PP_DEV_CONFIG (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/media/platform/verisilicon/
H A Dhantro_postproc.c40 .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
41 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
42 .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
43 .out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1},
H A Dhantro_g1_regs.h312 #define G1_REG_PP_DEV_CONFIG G1_SWREG(61) macro