Searched refs:EXYNOS5_DREXI_TIMINGDATA0 (Results 1 – 1 of 1) sorted by relevance
31 #define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) macro434 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()436 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()