Searched refs:ETHRX (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 117 #define ETHRX 104 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 117 #define ETHRX 104 macro
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp15xx-dhcom-som.dtsi | 461 * set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
462 * so that MCO2 behaves as a divider for the ETHRX clock here.
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| H A D | stm32mp151.dtsi | 1500 <&rcc ETHRX>,
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| /openbmc/linux/Documentation/devicetree/bindings/net/ |
| H A D | stm32-dwmac.yaml | 124 <&rcc ETHRX>,
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32mp1.c | 558 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32mp1.c | 1982 PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX),
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