Searched refs:DSA (Results 1 – 25 of 51) sorted by relevance
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130 CPU port can be configured to use either the DSA or the Ethertype DSA (EDSA)142 no DSA links in this fabric, and each switch constitutes a disjoint DSA switch143 tree. The DSA links are viewed as simply a pair of a DSA master (the out-facing145 downstream DSA switch).162 for the DSA master.187 Packet Steering) on the DSA master would be broken. The DSA framework deals307 device between the DSA slave devices and the physical DSA masters. The LAG308 device is thus also a DSA master, but the LAG slave devices continue to be DSA407 DSA does not currently create slave network devices for the CPU or DSA ports, as467 by DSA[all …]
4 DSA switch configuration from userspace7 The DSA switch configuration is not integrated into the main userspace15 To configure a DSA switch a couple of commands need to be executed. In this32 Through DSA every port of a switch is handled like a normal linux Ethernet42 - when a DSA slave interface is brought up, the master interface is329 # behaves the same for DSA as this command:338 such, will not forward it, as opposed to DSA.406 # See the DSA master in current use417 # CPU ports in LAG, using explicit assignment of the DSA master456 used as a DSA master; however, DSA will reject a LAG interface as a valid[all …]
41 The driver is located in ``drivers/net/dsa/bcm_sf2.c`` and is implemented as a DSA51 Overall, the SF2 driver is a fairly regular DSA driver; there are a few57 The DSA platform device driver is probed using a specific compatible string58 provided in ``net/dsa/dsa.c``. The reason for that is because the DSA subsystem gets59 registered as a platform device driver currently. DSA will provide the needed70 Broadcom switches connected to a SF2 require the use of the DSA slave MDIO bus74 "double" programming. Using DSA, and setting ``ds->phys_mii_mask`` accordingly, we
13 The driver is implemented as a DSA driver, see ``Documentation/networking/dsa/dsa.rst``.21 interfaces (which is the default state of a DSA device). Due to HW limitations,
17 DSA driver; see ``Documentation/networking/dsa/dsa.rst`` for details on the36 DSA driver and will work like all DSA drivers which supports tagging.
7 title: Generic DSA Switch Port15 A DSA switch port is a component of a switch that manages one MAC, and can17 DSA-specific functionality.34 Should be a list of phandles to other switch's DSA port. This62 # CPU and DSA ports must have phylink-compatible link descriptions
28 A two element list indicates which DSA cluster, and position within the38 description: A DSA switch without any extra port properties
21 Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is
1 Marvell DSA Switch Device Tree Bindings
43 and subnodes of DSA switches.
7 tagging protocol used by the DSA network devices that are10 attached DSA switches, if this operation is supported by the11 driver. Changing the tagging protocol must be done with the DSA
7 perf_event_attr.config1 for the IDXD DSA pmu. (See also13 IDXD DSA Spec for possible attribute values)::29 IDXD DSA pmu is bound for access to all dsa pmu
11 DSA, enumerator55 {SSHKeyType::DSA, "DSA"},
32 the SJA1105 DSA driver.41 engine in the SJA1105 DSA driver, which is controlled using a
4 NSS=Flags=internal,critical trustOrder=75 cipherOrder=100 slotParams=(1={slotFlags=[ECC,RSA,DSA,DH,…
76 tristate "Tag driver for Marvell switches using DSA headers"80 Marvell switches which use DSA headers.83 tristate "Tag driver for Marvell switches using EtherType DSA headers"87 Marvell switches which use EtherType DSA headers.
634 3.2.1 DSA (Distributed Switch Architecture) switches639 a port multiplier with optional forwarding acceleration features. Each DSA644 When a DSA switch is attached to a host port, PTP synchronization has to646 jitter between the host port and its PTP partner. For this reason, some DSA649 measure wire and PHY propagation latencies. Timestamping DSA switches are653 interfaces of a DSA switch to share the same PHC.655 By design, PTP timestamping with a DSA switch does not need any special663 In the generic layer, DSA provides the following infrastructure for PTP691 - ``.port_rxtstamp()``: On RX, the BPF classifier is run by DSA to697 DSA header, or attached in other ways to the packet), or out-of-band[all …]
3 and DSA certificates)"
11 Example using the old DSA DeviceTree binding:
1 Hisilicon DSA Fabric device controller12 - interrupts: should contain the DSA Fabric and rcb interrupt.
50 The read buffers represent resources within the DSA52 support operations. See DSA spec v1.2 9.2.4 Total Read Buffers.127 device. See DSA spec v1.2 9.2.8 GENCFG on Global Read Buffer Limit.283 Description: Enable the use of global read buffer limit for the group. See DSA293 by all engines in the group. See DSA spec v1.2 9.2.18 GRPCFG Read303 engines in the group. See DSA spec v1.2 9.2.18 GRPCFG Read Buffers
24 used by switchdev as well as by DSA drivers.
20 tristate "DSA mock-up Ethernet switch chip support"25 exercises the DSA APIs.
192 * BCM53134 is added to "bcm53xx" DSA driver.
93 * of Realtek DSA switch on the board.