Searched refs:DRX_CFG_BASE (Results 1 – 1 of 1) sorted by relevance
896 #ifndef DRX_CFG_BASE897 #define DRX_CFG_BASE 0 macro900 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */901 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */902 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */903 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */904 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */905 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */906 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */907 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */[all …]