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Searched refs:DP_DSC_CNTL (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.c287 REG_UPDATE_2(DP_DSC_CNTL, in enc2_dp_set_dsc_config()
356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
358 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
H A Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c395 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc32_dp_set_dsc_config()
406 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
H A Ddcn32_resource.h294 SRI_ARR(DP_SEC_TIMESTAMP, DP, id), SRI_ARR(DP_DSC_CNTL, DP, id), \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c390 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc314_dp_set_dsc_config()
401 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
H A Ddcn314_dio_stream_encoder.h100 SRI(DP_DSC_CNTL, DP, id), \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_stream_encoder.c313 REG_UPDATE_2(DP_DSC_CNTL, in enc3_dp_set_dsc_config()
395 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
397 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc3_read_state()
H A Ddcn30_dio_stream_encoder.h101 SRI(DP_DSC_CNTL, DP, id), \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.h177 uint32_t DP_DSC_CNTL; member