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Searched refs:DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_0_sh_mask.h2122 #define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 macro
H A Dsmu_7_0_1_sh_mask.h2122 #define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8 macro