/openbmc/linux/drivers/gpu/drm/i915/ |
H A D | intel_gvt_mmio_table.c | 1123 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY0)); in iterate_bxt_mmio() 1131 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0)); in iterate_bxt_mmio() 1132 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0)); in iterate_bxt_mmio() 1133 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0)); in iterate_bxt_mmio() 1134 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0)); in iterate_bxt_mmio() 1135 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0)); in iterate_bxt_mmio() 1136 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0)); in iterate_bxt_mmio() 1137 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0)); in iterate_bxt_mmio() 1138 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0)); in iterate_bxt_mmio() 1139 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0)); in iterate_bxt_mmio() [all …]
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H A D | vlv_sideband.c | 225 return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO; in vlv_dpio_phy_iosf_port()
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H A D | i915_reg.h | 1469 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
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/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_display_power_well.c | 1320 if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status() 1322 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | in assert_chv_phy_status() 1323 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | in assert_chv_phy_status() 1324 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | in assert_chv_phy_status() 1325 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | in assert_chv_phy_status() 1326 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); in assert_chv_phy_status() 1334 phy_status |= PHY_POWERGOOD(DPIO_PHY0); in assert_chv_phy_status() 1347 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status() 1423 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_enable() 1486 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_disable() [all …]
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H A D | intel_dpio_phy.h | 24 DPIO_PHY0, enumerator
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H A D | intel_dpio_phy.c | 165 [DPIO_PHY0] = { 187 [DPIO_PHY0] = { 268 *phy = DPIO_PHY0; in bxt_port_to_phy_channel() 663 return DPIO_PHY0; in vlv_dig_port_to_phy() 843 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); in chv_phy_pre_pll_enable() 991 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); in chv_phy_release_cl2_override()
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H A D | intel_display_power.c | 1765 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | in chv_phy_control_init() 1767 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | in chv_phy_control_init() 1768 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | in chv_phy_control_init() 1787 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); in chv_phy_control_init() 1790 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); in chv_phy_control_init() 1797 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); in chv_phy_control_init() 1800 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); in chv_phy_control_init() 1802 dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init() 1804 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init() 1806 dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
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H A D | intel_display_power_map.c | 483 .bxt.phy = DPIO_PHY0, 587 .bxt.phy = DPIO_PHY0,
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/openbmc/linux/drivers/gpu/drm/i915/gvt/ |
H A D | display.c | 235 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in emulate_monitor_status_change() 239 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30); in emulate_monitor_status_change() 298 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change() 300 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change() 328 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in emulate_monitor_status_change() 330 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |= in emulate_monitor_status_change()
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H A D | mmio.c | 264 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in intel_vgpu_reset_mmio() 268 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= in intel_vgpu_reset_mmio()
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H A D | handlers.c | 539 enum dpio_phy phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate() 551 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate() 555 phy = DPIO_PHY0; in bxt_vgpu_get_dp_bitrate() 1879 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= in bxt_gt_disp_pwron_write() 1881 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= in bxt_gt_disp_pwron_write() 2754 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, in init_bxt_mmio_info() 2765 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info() 2767 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, in init_bxt_mmio_info() 2769 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info() 2771 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, in init_bxt_mmio_info()
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