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Searched refs:DMA_CSR (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/scsi/
H A Dsun_esp.c240 val = dma_read32(DMA_CSR); in sbus_esp_reset_dma()
276 dma_write32(0, DMA_CSR); in sbus_esp_reset_dma()
290 val = dma_read32(DMA_CSR); in sbus_esp_reset_dma()
297 dma_write32(val, DMA_CSR); in sbus_esp_reset_dma()
301 val = dma_read32(DMA_CSR); in sbus_esp_reset_dma()
309 dma_write32(val, DMA_CSR); in sbus_esp_reset_dma()
317 val = dma_read32(DMA_CSR); in sbus_esp_reset_dma()
329 csr = dma_read32(DMA_CSR); in sbus_esp_dma_drain()
357 dma_write32(0, DMA_CSR); in sbus_esp_dma_invalidate()
380 dma_write32(val, DMA_CSR); in sbus_esp_dma_invalidate()
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H A Dsun3x_esp.c75 val = dma_read32(DMA_CSR); in sun3x_esp_reset_dma()
76 dma_write32(val | DMA_RST_SCSI, DMA_CSR); in sun3x_esp_reset_dma()
80 val = dma_read32(DMA_CSR); in sun3x_esp_reset_dma()
81 dma_write32(val | DMA_INT_ENAB, DMA_CSR); in sun3x_esp_reset_dma()
89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
123 dma_write32(val, DMA_CSR); in sun3x_esp_dma_invalidate()
125 dma_write32(val, DMA_CSR); in sun3x_esp_dma_invalidate()
137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
151 u32 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_error()
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/openbmc/linux/drivers/net/ethernet/amd/
H A Dsunlance.c436 u32 csr = sbus_readl(lp->dregs + DMA_CSR); in init_restart_ledma()
444 csr = sbus_readl(lp->dregs + DMA_CSR); in init_restart_ledma()
458 sbus_writel(csr, lp->dregs + DMA_CSR); in init_restart_ledma()
494 u32 csr = sbus_readl(lp->dregs + DMA_CSR); in init_restart_lance()
497 sbus_writel(csr, lp->dregs + DMA_CSR); in init_restart_lance()
856 u32 dma_csr = sbus_readl(lp->dregs + DMA_CSR); in lance_interrupt()
859 sbus_writel(dma_csr, lp->dregs + DMA_CSR); in lance_interrupt()
986 csr = sbus_readl(lp->dregs + DMA_CSR); in lance_reset()
987 sbus_writel(csr | DMA_RST_ENET, lp->dregs + DMA_CSR); in lance_reset()
1434 csr = sbus_readl(lp->dregs + DMA_CSR); in sparc_lance_probe_one()
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/openbmc/linux/arch/sparc/include/asm/
H A Ddma.h18 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ macro