Home
last modified time | relevance | path

Searched refs:DDR_CL (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h427 #define DDR_CL 6 macro
429 #define DDR_tCWL (DDR_CL - 1)
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c46 tmp = DDR_CL; in ddr_cfg_init()