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Searched refs:CP_RB1_CNTL__CACHE_POLICY_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2742 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L macro
H A Dgfx_7_2_sh_mask.h1085 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000 macro
H A Dgfx_8_0_sh_mask.h1403 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 macro
H A Dgfx_8_1_sh_mask.h1927 #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10941 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_9_2_1_sh_mask.h12226 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_9_1_sh_mask.h12422 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_9_4_3_sh_mask.h13951 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_9_4_2_sh_mask.h2242 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_11_0_0_sh_mask.h15373 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_11_0_3_sh_mask.h17528 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_10_1_0_sh_mask.h17871 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro
H A Dgc_10_3_0_sh_mask.h16133 #define CP_RB1_CNTL__CACHE_POLICY_MASK macro