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Searched refs:CP_PQ_WPTR_POLL_CNTL__EN_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h1485 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 macro
H A Dgfx_8_0_sh_mask.h1915 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 macro
H A Dgfx_8_1_sh_mask.h2437 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11264 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h12529 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_9_1_sh_mask.h12744 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_9_4_3_sh_mask.h14471 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_9_4_2_sh_mask.h2664 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_11_0_0_sh_mask.h15750 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_11_0_3_sh_mask.h17941 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h18233 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h16581 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK … macro