Searched refs:CLK_DIV_GDL (Results 1 – 8 of 8) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | exynos4.h | 238 #define CLK_DIV_GDL 459 macro
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| H A D | exynos3250.h | 84 #define CLK_DIV_GDL 65 macro
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| /openbmc/linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | samsung,exynos-bus.yaml | 271 clocks = <&cmu CLK_DIV_GDL>;
300 clocks = <&clock CLK_DIV_GDL>;
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| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos4210.dtsi | 134 clocks = <&clock CLK_DIV_GDL>;
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| H A D | exynos4x12.dtsi | 116 clocks = <&clock CLK_DIV_GDL>;
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| H A D | exynos3250.dtsi | 125 clocks = <&cmu CLK_DIV_GDL>;
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-exynos3250.c | 342 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
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| H A D | clk-exynos4.c | 594 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
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