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Searched refs:CLK_DIV_CPU1_VAL (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c63 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); in system_clock_init()
H A Dexynos4_setup.h63 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) macro
H A Dexynos5_setup.h123 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ macro
H A Dclock_init_exynos5.c612 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); in exynos5250_system_clock_init()
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c323 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); in board_clock_init()
H A Dsetup.h48 #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) macro