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Searched refs:CLE (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/hw/block/
H A Dtc58128.c39 #define CLE 0x2000 macro
180 if (porta & CLE) { in tc58128_cb()
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dgpio-control-nand.txt15 GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
41 <&banka 4 0>, /* CLE */
H A Dorion-nand.txt9 - cle : Address line number connected to CLE. Default is 0
H A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
H A Ddavinci-nand.txt33 - ti,davinci-mask-cle: mask for CLE. Needed for executing command
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead-sharpsl.S136 bic r3, r3, #2 @ CLR CLE
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-tse850-3.dts359 /* 20 */ "", "ALE", "CLE", "",
H A Dsama5d4.dtsi1279 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
/openbmc/linux/arch/powerpc/boot/dts/
H A Dxpedite5200.dts431 cle-line = <0x8>; /* CLE tied to A3 */
H A Dxpedite5200_xmon.dts435 cle-line = <0x8>; /* CLE tied to A3 */
/openbmc/linux/Documentation/driver-api/
H A Dmtdnand.rst164 case NAND_CTL_SETCLE: /* Set CLE pin high */ break;
165 case NAND_CTL_CLRCLE: /* Set CLE pin low */ break;
908 /* Select the command latch by setting CLE to high */
910 /* Deselect the command latch by setting CLE to low */
/openbmc/linux/Documentation/driver-api/gpio/
H A Ddrivers-on-gpio.rst79 to a set of simple GPIO lines: RDY, NCE, ALE, CLE, NWP. It interacts with the
/openbmc/linux/arch/mips/boot/dts/ingenic/
H A Dci20.dts427 * Only CLE/ALE are needed for the devices that are connected, rather
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d4.dtsi1738 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */