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Searched refs:CGTS_CU5_SP0_CTRL_REG__SP01_MASK (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h9821 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
H A Dgfx_8_0_sh_mask.h11545 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
H A Dgfx_8_1_sh_mask.h11943 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h24450 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_2_1_sh_mask.h25872 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_1_sh_mask.h25741 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_4_3_sh_mask.h28257 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro
H A Dgc_9_4_2_sh_mask.h18162 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK … macro