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Searched refs:CCM_PLL5_CTRL_M (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c257 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); in mctl_setup_dram_clock()
262 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); in mctl_setup_dram_clock()
267 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3)); in mctl_setup_dram_clock()
272 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); in mctl_setup_dram_clock()
277 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); in mctl_setup_dram_clock()
282 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2)); in mctl_setup_dram_clock()
H A Dclock_sun6i.c211 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); in clock_set_pll5()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun4i.h216 #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) macro
217 #define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
H A Dclock_sun6i.h222 #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) macro