Home
last modified time | relevance | path

Searched refs:BUSIF_WR_CG_EN (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h408 #define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */ macro
411 BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)