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Searched refs:ARM_CP_STATE_AA64 (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcortex-regs.c30 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
38 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
47 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
53 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
59 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
65 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
H A Dcpregs-pmu.c1030 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
1043 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1057 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1070 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
1082 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
1088 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1102 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1115 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
1126 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
1137 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
[all …]
H A Ddebug_helper.c961 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
980 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
999 { .name = "DBGDTRTX_EL0", .state = ARM_CP_STATE_AA64,
1008 { .name = "DBGDTR_EL0", .state = ARM_CP_STATE_AA64,
1115 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,