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Searched refs:ARM_CP_NOP (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/arm/
H A Dhelper.c490 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
492 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
494 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
496 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
500 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
543 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, in cpacr_write()
545 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, in cpacr_write()
656 .access = PL1_W, .type = ARM_CP_NOP },
660 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
665 .access = PL0_W, .type = ARM_CP_NOP },
[all...]
H A Dcpregs.h39 ARM_CP_NOP = 0x0001,
38 ARM_CP_NOP = 0x0001, global() enumerator
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
585 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
705 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
708 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
711 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
714 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
717 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
720 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
H A Dtlb-insns.c1222 .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
1225 .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
1228 .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS },
1231 .access = PL2_W, .type = ARM_CP_NOP | ARM_CP_ADD_TLBI_NXS }, in tlbi_aa64_paall_write()
H A Dtranslate.c1861 case ARM_CP_NOP: in disas_iwmmxt_insn()
H A Dtranslate-a64.c2970 case ARM_CP_NOP: in gen_store_exclusive()