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Searched refs:TLB (Results 51 – 75 of 161) sorted by relevance

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/openbmc/linux/Documentation/translations/zh_CN/arch/openrisc/
H A Dopenrisc_port.rst109 彻底改变TLB失误处理。
/openbmc/linux/Documentation/mm/
H A Dhighmem.rst23 VM space so that we don't have to pay the full TLB invalidation costs for
147 requires global TLB invalidation when the kmap's pool wraps and it might
172 manipulate the kernel's page tables, the data TLB and/or the MMU's registers.
198 data has to be accessed to traverse in TLB fills and the like. One
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex419 % IA32/x64 Processor Error Check Info (Cache/TLB Error)
420 \subsection{IA32/x64 Processor Error Check Info (Cache/TLB Error) Structure}
433 level & uint64 & The cache/TLB level at which the error occurred.\\
809 % ARM Processor Error Info Error Information (Cache/TLB) structure
810 \subsection{ARM Processor Error Info Cache/TLB Information Structure}
816 transactionType.value & uint64 & The raw value of the type of cache/TLB error.\\
822 level & int & The cache/TLB level that the error occurred at.\\
831 \jsontableend{ARM Processor Error Info Cache/TLB Information structure field table.}
833 % ARM Processor Error Info Error Information (Cache/TLB) validation structure
834 \subsection{ARM Processor Error Info Cache/TLB Validation Structure}
[all …]
/openbmc/linux/arch/x86/events/intel/
H A Dds.c178 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
190 val |= P(TLB, MISS); in precise_store_data()
192 val |= P(TLB, HIT); in precise_store_data()
249 *val |= P(TLB, MISS) | P(TLB, L2); in pebs_set_tlb_lock()
251 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in pebs_set_tlb_lock()
318 val |= P(TLB, NA) | P(LOCK, NA); in load_latency_data()
/openbmc/linux/Documentation/powerpc/
H A Dkaslr-booke32.rst15 parts expect lowmem to be mapped by fixed TLB entries(TLB1). The TLB1
/openbmc/linux/arch/arm64/kvm/
H A Dnested.c37 val &= ~(NV_FTR(ISAR0, TLB) | in access_nested_id_reg()
/openbmc/linux/Documentation/arch/x86/
H A Dsva.rst25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
79 the device TLB in sync. For example, when a page-table entry is invalidated,
80 the IOMMU propagates the invalidation to the device TLB. This will force any
258 Device TLB support - Device requests the IOMMU to lookup an address before
270 device TLB entry that might have been cached before removing the mappings from
/openbmc/u-boot/doc/
H A DREADME.srio-pcie-boot-corenet74 i) Slave will set a specific TLB entry for the boot process.
77 k) Slave will set a specific TLB entry in order to fetch UCode and ENV
/openbmc/linux/tools/perf/util/
H A Dparse-events.l171 …ata|L1-icache|l1-i|l1i|L1-instruction|LLC|L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch…
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dentry.S92 ! TLB Miss / Initial Page write exception handling
94 ! TLB hits, but the access violate the protection.
/openbmc/linux/Documentation/gpu/rfc/
H A Di915_vm_bind.rst33 TLB flush consideration
35 The i915 driver flushes the TLB for each submission and when an object's
37 TLB flush. Any VM_BIND mapping added will be in the working set for subsequent
39 batches (which would require additional TLB flushes, which is not supported).
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S35 ! TI == TLB Invalidate bit
/openbmc/linux/arch/arm/mm/
H A DKconfig147 instruction sequences for cache and TLB operations. Curiously,
166 Branch Target Buffer, Unified TLB and cache line size 16.
570 # This selects the TLB model
574 ARM Architecture Version 4 TLB with writethrough cache.
579 ARM Architecture Version 4 TLB with writeback cache.
584 ARM Architecture Version 4 TLB with writeback cache and invalidate
590 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
595 Faraday ARM FA526 architecture, unified TLB with writeback cache
611 tag TLB and possibly cache entries.
/openbmc/qemu/docs/system/arm/
H A Demulation.rst99 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
100 - FEAT_TLBIRANGE (TLB invalidate range instructions)
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml147 /* DTLB_READ_MISS -> Data TLB miss */
149 /* ITLB_READ_MISS-> Instruction TLB miss */
/openbmc/linux/Documentation/admin-guide/mm/
H A Dtranshuge.rst36 1) the TLB miss will run faster (especially with virtualization using
40 2) a single TLB entry will be mapping a much larger amount of virtual
41 memory in turn reducing the number of TLB misses. With
42 virtualization and nested pagetables the TLB can be mapped of
45 the two is using hugepages just because of the fact the TLB miss is
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
H A Dsamsung,sysmmu.yaml20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Network/Experimental/
H A DBond.interface.yaml52 - name: TLB
/openbmc/linux/drivers/iommu/
H A DKconfig110 DMA-mapped pages, with strict TLB invalidation on unmap. Equivalent
121 DMA-mapped pages, but with "lazy" batched TLB invalidation. This
122 mode allows higher performance with some IOMMUs due to reduced TLB
387 Say Y here to enable debug for issues such as TLB sync timeouts
/openbmc/qemu/docs/system/i386/
H A Dkvm-pv.rst61 Enable paravirtualized TLB flush mechanism. Supported since Linux v4.16.
/openbmc/linux/arch/sparc/kernel/
H A Dktlb.S173 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
/openbmc/linux/tools/perf/Documentation/
H A Ditrace.txt18 t synthesize TLB events
/openbmc/u-boot/arch/nds32/cpu/n1213/
H A Dstart.S516 li $p1, 0x2 ! TLB MMU
518 tlbop flushall ! Flush TLB
/openbmc/linux/Documentation/kernel-hacking/
H A Dfalse-sharing.rst66 cache hot and save cacheline/TLB, like a lock and the data protected
148 cache line and TLB entries.

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