/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | motorcomm,yt8xxx.yaml | 23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with 58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can 75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can 97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII 103 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII 109 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
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H A D | xlnx,gmii-to-rgmii.yaml | 7 title: Xilinx GMII to RGMII Converter 14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
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H A D | adi,adin.yaml | 21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with 28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
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H A D | mediatek-dwmac.yaml | 79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170, 83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290, 89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170, 93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple 112 1. tx clock will be inversed in MII/RGMII case, 122 1. rx clock will be inversed in MII/RGMII case.
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H A D | ibm,emac.txt | 5 special McMAL DMA controller, and sometimes an RGMII or ZMII 55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle 56 of the RGMII device node. 58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which 59 RGMII channel is used by this EMAC. 195 iv) RGMII node 203 - revision : as provided by the RGMII new version register if
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H A D | ingenic,mac.yaml | 44 description: RGMII receive clock delay defined in pico seconds 47 description: RGMII transmit clock delay defined in pico seconds
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H A D | ti,dp83869.yaml | 21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and 24 conversions. The DP83869HM can also support Bridge Conversion from RGMII to 25 SGMII and SGMII to RGMII.
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H A D | ti,dp83867.yaml | 25 Media Independent Interface (GMII) or Reduced GMII (RGMII). 81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h 88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
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H A D | ethernet-controller.yaml | 81 # RGMII with internal RX and TX delays provided by the PHY, 85 # RGMII with internal RX delay provided by the PHY, the MAC 89 # RGMII with internal TX delay provided by the PHY, the MAC 278 RGMII Receive Clock Delay defined in pico seconds.This is used for 283 RGMII Transmit Clock Delay defined in pico seconds.This is used for
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H A D | apm-xgene-enet.txt | 8 - "apm,xgene-enet": RGMII based 1G interface 42 - tx-delay: Delay value for RGMII bridge TX clock. 46 - rx-delay: Delay value for RGMII bridge RX clock.
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/openbmc/linux/include/dt-bindings/phy/ |
H A D | phy-lan966x-serdes.h | 10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro 11 #define RGMII_MAX RGMII(2)
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | starfive,jh7110-aoncrg.yaml | 23 - description: GMAC0 RMII reference or GMAC0 RGMII RX 30 - description: GMAC0 RMII reference or GMAC0 RGMII RX 31 - description: STG AXI/AHB or GMAC0 RGMII RX 39 - description: GMAC0 RGMII RX
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H A D | starfive,jh7110-syscrg.yaml | 23 - description: GMAC1 RMII reference or GMAC1 RGMII RX 37 - description: GMAC1 RGMII RX
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | ti,dp83867.txt | 5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h 7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | microchip,lan966x-serdes.yaml | 14 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII. 20 following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
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/openbmc/u-boot/include/configs/ |
H A D | tqma6_mba6.h | 12 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | zc5601.h | 23 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | platinum_titanium.h | 18 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | aristainetos2b.h | 21 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | aristainetos2.h | 21 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | secomx6quq7.h | 31 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | mx6qarm2.h | 25 #define CONFIG_FEC_XCV_TYPE RGMII
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H A D | sksimx6.h | 25 #define CONFIG_FEC_XCV_TYPE RGMII
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/openbmc/u-boot/doc/ |
H A D | README.fec_mxc | 12 RGMII selects 1000 Base-tx reduced pin count interface. 33 example if the CPU is connected directly via the RGMII interface to a
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/openbmc/u-boot/board/freescale/bsc9131rdb/ |
H A D | README | 28 . eTSEC 1 supports RGMII/RMII 29 . eTSEC 2 supports RGMII 69 eTSEC1: Connected to RGMII PHY 70 eTSEC2: Connected to RGMII PHY
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